The use of Time Division Multiple Access ("TDMA") and Digital Speech Interpolation ("DSI") techniques have proven useful for optimizing the transmission and receiving capabilities of various communication systems. DSI is particularly useful in telephony systems because it allows the system to take advantage of the silent intervals in normal speech patterns. Application of these techniques provides for a more efficient transfer of data between the various units of a system, for example a cellular telephone system comprising a base station and remote units. The techniques also provide for a more efficient transfer of data between different modules contained within a single unit.
Such systems typically allow each unit to access or transmit data for a portion of time within a periodic cycle, hereinafter referred to as a TDMA cycle. The minimum duration of the TDMA cycle is a function of system requirements, for example, the number of units which need to transmit or receive data each cycle.
With regard to the transfer of data between a plurality of modules within a single unit, it is desirable to transfer the data between the modules as fast as possible. If the time allocated for data transfer in a predefined TDMA cycle is minimized there are numerous benefits. For example, more time can be allocated for processing data, or alternatively, the minimum duration of the TDMA cycle can be decreased.
Heretofore, systems utilized "busy" or "semaphore" arbitration to determine whether a digital signal processor ("DSP") contained on a module or the memory associated therewith, was available to transmit or receive data from another module. However, the "busy" and "semaphore" arbitration schemes require the transmitting/receiving module to request access to the destination module, and then wait for a reply from the destination module, prior to sending or retrieving data. If the destination module is presently unavailable, the data transfer request must be either held open or forwarded again. In the case of digital signal processors or RISC processors which typically have short instructions cycle periods, wait states may have to be inserted for any dual port random access memory ("RAM") devices to accommodate valid "busy" timing. Additionally, buffering delays associated with multiple modules interfaced by way of a common backplane can also require additional wait states to accommodate dual port RAM "busy" timing. Thus, such arbitration schemes utilize a portion of the TDMA cycle to determine if data can be transferred between modules and, as a result, the overall processing efficiency of the system is reduced.
Accordingly, there exists a need for a device for transferring data between modules of a single unit which does not allocate any portion of the TDMA cycle to requesting or verifying whether or not the selected module is ready to process the data transfer request, as well as a device which minimizes the time necessary for transferring data between the modules.